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Application Note 9725
identical two-bit subconverter stages with the corresponding
Φ 1
C H
Φ 1
output of the ninth stage flash converter before applying the
eighteen bit result to the digital error correction logic. The
V IN+
V IN-
Φ 1
Φ 2
Φ 1
C S
C S
Φ 1
- +
+ -
C H
Φ 1
V OUT+
V OUT-
digital error correction logic uses the supplementary bits to
correct any error that may exist before generating the final ten
bit digital data output of the converter.
Because of the pipeline nature of this converter, the digital data
representing an analog input sample is output to the digital data
bus on the 7th cycle of the clock after the analog sample is
taken. This time delay is specified as the data latency. After the
data latency time, the digital data representing each
succeeding analog sample is output during the following clock
FIGURE 1. ANALOG INPUT SAMPLE-AND-HOLD
The output of each of the eight identical two-bit subconverter
stages is a two-bit digital word containing a supplementary bit
to be used by the digital error correction logic. The output of
each subconverter stage is input to a digital delay line which is
controlled by the internal sampling clock. The function of the
digital delay line is to time align the digital outputs of the eight
ANALOG
INPUT
cycle. The digital output data is synchronized to the external
sampling clock by a double buffered latching technique. The
output of the digital error correction circuit is available in two’s
complement or offset binary format depending on the state of
the Data Format Select (DFS) control input (see HI5746 Data
Sheet Table 1, A/D Code Table).
CLOCK
INPUT
S N-1
H N-1
S N
H N
S N+1
H N+1
S N+2
S N+5
H N+5
S N+6
H N+6
S N+7
H N+7
S N+8
H N+8
INPUT
S/H
1ST
STAGE
2ND
STAGE
9TH
STAGE
DATA
OUTPUT
B 2, N-2
B 1, N-1
B 9, N-5
D N-6
B 2, N-1
B 1, N
B 9, N-4
D N-5
B 2, N
B 1, N+1
B 9, N-3
D N-4
B 1, N+4
B 9, N
D N-1
B 2, N+4
B 1, N+5
B 9, N+1
D N
B 2, N+5
B 1, N+6
B 9 N+2
D N+1
B 2, N+6
B 1, N+7
B 9, N+3
D N+2
NOTES:
t LAT
1. S N : N-th sampling period.
2. H N : N-th holding period.
3. B M, N : M-th stage digital output corresponding to N-th sampled input.
4. D N : Final data output corresponding to N-th sampled input.
FIGURE 2. HI5746 INTERNAL CIRCUIT TIMING
3-3
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